HC(S)08 vs. Cortex M0


Back in the 1980s, Motorola introduced the HC08 family of 8-bit microcontrollers. A direct descendant of the HC05 (which, in turn, was a direct descendant of the 6800 microprocessor), it extended its memory space from 256 bytes to 65,536 bytes, creating an 8-bit microcontroller with a 16-bit direct-paged memory map. A few decades later, Freescale (which is also a direct descendant of Motorola) improved power consumption, made the silicon node smaller, added an on-chip debugger, and re-launched the family as the S08. With a few decades in its track-record, the HC(S)08 can only be considered a commercial success. Even today, the small 8-bit microcontrollers succeed in finding new applications.

The world, however, is a different place than what it was in the 1980s. With the incredible success the ARM platform has had in recent years, one is forced to ask itself if its not time for older 8-bit architectures to find their place in museums and stories old people like to tell to younger generations. Is the Cortex M0 a viable replacement for 8-bit legacy architectures, namely the HC(S)08?

To help answer this question, we’ve selected a reprensentative from each side. The 80-pin 9s08QE128 represents the legacy base option, while NXP’s 100-pin, 128kB version of the LPC1200 microcontroller represents the post-modern solution.


First things first. Before even thinking of replacing a simple, proven, to-the-point solution, one must ask if the replacement part has a similar cost. Unit price at Digikey is used for these purposes, and presented in Table 1.

9s08QE128 LPC1200 Units Delta (ABS) Delta (%) Best Criteria Winner
Unit Price 5.27 6.13 USD 0.86 14 < 9s08QE128
Table 1. Data accessed on 15-May-2012.

For all practical purposes, we’ll assume that a 14% price difference for 4-times the number of processing bits shall be considered comparable… But what about the technical stuff?


Table 2 shows a summary of all available peripherals on both devices.

9s08QE128 LPC1200 Units Delta (ABS) Delta (%) Best Criteria Winner
ADC 10-bit 10-bit 10-bit Equal
UART 2 2 0 0 > Equal
SPI 2 1 1 50 > 9s08QE128
IIC 2 1 1 50 > 9s08QE128
External IRQ sources 16 55 39 70.90909091 > LPC1200
Timer units 3 2 1 33.33333333 > 9s08QE128
Watch-dog 1 1 0 0 > Equal
Real-time clock 1 1 0 0 > Equal
Table 2.

The LPC1200 includes a hard-CRC and a mini-DMA module that are most welcomed. However, the 9S08QE128 has a double-count for UARTs, SPI and IIC ports. The bottom line is that the sheer number of peripherals don’t necessarily make a microcontroller a better choice than another, but they may certainly come in handy in a given application. There is no clear-cut winner in this case, but the DMA and CRC modules are a big plus.

Power Consumption Differences

Table 3 compares and contrasts power consumption number for both devices. For the S08, STOP2 and STOP3 modes are used; for its ARM counter-part, SLEEP and DEEP-SLEEP modes are used.

9s08QE128 LPC1200 Units Delta (ABS) Delta (%) Best Criteria Winner
RUN mode Typical Idd @ full speed 16 14.1 mA 1.9 11.875 < LPC1200
Mid-Sleep mode Typical Idd @ full clock 0.00098 4.4 mA 4.39902 99.97772727 < 9s08QE128
Full sleep mode Typical Idd 2 30 uA 28 93.33333333 < 9s08QE128
Table 3.

Note that during code execution, the NXP product is slightly better than the Freescale one. However, most embedded applications spend most of their time in a no-code-execution state, making the latter significantly more attractive. Although there is no clear-cut winner (again), the 9S08 seems to have a better overall performance.

Core Architecture & Code execution

Table 4 presents a combination of data that compares both architectures. It’s important to mention that while the S08 family has been designed from the start to be a microcontroller, the LM1200 actually implements a SoC with an ARM v6  processor within. This leverages the power of the existing architecture, but adds complexity to the programmers model.

9s08QE128 LPC1200 Units Delta (ABS) Delta (%) Best Criteria Winner
Memory Architecture Von Neumann Von Neumann Harvard Equal
Architecture CISC 3-stage pipeline 3-stage pipeline LPC1200
Process node 250 90 nm 160 64 < LPC1200
Multiply operation cycles 11 3 cycles 8 72.7272 < LPC1200
Complexity Low Medium Low 9s08QE128
OS native support N Y Y LPC1200
Table 4.

Perhaps the most relevant fields presented in Table 4 are “Architecture” and “Multiply operation cycles.”

“Architecture” demonstrates a pipelined approach for the ARM-based contender. This modern solution allows a 1-cycle-per-op-code operation cycle for most instructions, while the CISC approach from the S08 family allows for variable execution times per op-code.

The result shows of this architectural decision is presented in the “Multiply operation cycles.” What is actually being compared is the number of clock-cycles required to to execute a native multiply operation, including a load register(s) and store result operation. Not taken into account is the fact that the ARM core will perform a 32-bit multiplication, while the 9S08 will only perform an 8-bit operation.

In this arena, it is clear that the LPC1200 is a more mature solution, and even though development times for it may take longer, it takes the cake.


The data presented here is a very high-level comparison with no specific application in mind. The LPC1200, on one hand, shows a modern core with operation-unloading peripherals; the 9S08QE128 presents a simple programming model with excellent power consumption and tons of peripherals for a lower price. It is, hence, impossible to dismiss the 8-bit machine as a ghost from the past, but it is also impossible to state that the 32-bit machine is attractive for modern-day applications. The choice, therefore, will depend greatly on the application, and on the developer’s programming experience.





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